1. Field of the Invention
The present invention relates to a semiconductor memory such as a ROM (Read Only Memory) storing multi-level data, and more particularly to an apparatus and method for reading multi-value data from a ROM.
2. Description of the Related Art
The memory-cell array of, for example, a ROM comprises memory cells arranged in rows and columns. Word lines extend along the rows of memory cells, and bit lines extend along the columns of memory cells. Each memory cell has its gate connected to a word line and its source and drain connected to a bit line. To read data from any desired memory cell, the bit line to which the desired memory cell is connected is selected, and the world line to which the desired memory cell is connected is set at a high level.
Generally, a one-bit memory cell has one transistor. The threshold voltage of the transistor is set at a high or low level so that the memory cell stores data. The memory cell can store but one bit of data at a time. To store a great amount of data, a memory needs to have many cells, and its chip size inevitably becomes large.
To manufacture a memory which can store a large amount of data without increasing its chip size, it has recently been proposed that two bits of data be stored in one memory cell. Such a memory is called "multi-level memory." Various types of multi-level memories may be provided. In one type, the gate length or gate width of the transistor of each memory cell is changed so that the current flowing when the memory cell is selected may be set at various values. In another type, the dose of impurity ions injected into the MOS transistor of each memory cell is changed so that the threshold voltage of the MOS transistor may be set at various values. Thus, each memory cell of a multi-level memory can store two or more bits when set in two or more states. The multi-level memory has therefore an increased storage capacity of the memory.
FIG. 48 illustrates the relationship between the gate voltage Vg and drain current Id of each of the memory cells constituting a multi-level ROM. Each memory cell of this multi-level ROM has one of four different threshold voltages V1 to V4 and can store two bits of data. The threshold voltages V1 to V4 have the relationship of: V1&lt;V2&lt;V3&lt;V4. Any memory cell having threshold voltage V1 will be identified as memory cell MOO; any memory cell having threshold voltage V2 as memory cell M01; any memory cell having threshold voltage V3 as memory cell M10; and any memory cell having threshold voltage V4 as memory cell M11. The memory cells M00, M01, M10 and M11 are assumed to store data items "00", "01", "10" and "11", respectively.
FIG. 49 is a circuit diagram showing a conventional multi-level ROM. The memory cell array 1 of the ROM has memory cells M1, M2 . . . which are MOS transistors and which are arranged in rows and column. Word lines W1, W2, W3, . . . extend along the rows of memory cells, and bit lines B1, B2, . . . and B4 and bit lines B5, B6 . . . B8 extend along the columns of memory cells. Each memory cell has its gate connected to a word line and its drain connected to a bit line. The source of each the memory cell is grounded. The word lines W1, W2, W3, . . . are connected to a row decoder 2.
The multi-level ROM has a first set of selecting transistors S11, S12, . . . and S21, S22, . . . , a second set of selecting transistors S1, S2, . . . , a first set of bit-selecting lines L1, L2, . . . L4, and a second set of bit-selecting lines C1, C2, . . .
The bit lines B1, B2, . . . B4 are connected to a main bit line MB1 by selecting transistors S11, S12, . . . S14. The bit lines B5, B6, . . . B8 are connected to a main bit line MB2 by selecting transistors S21, S22 . . . S24. The gates of the selecting transistors S11, S12, S14, S21, S22, . . . S24 are connected to the bit-selecting lines L1, L2, . . . L4, respectively. The bit-selecting lines L1 to L4 are connected to a column decoder 3. The main bit lines MB1 and MB2 are connected by the selecting transistors S1, S2, . . . to the input SIN of a sense amplifier 5. The gates of the selecting transistors S1, S2, . . . are connected to the bit-selecting lines C1 and C2 . . . , which in turn are connected to a second column decoder 4. The output of the sense amplifier 5 is connected to the input of an output circuit 6. The output circuit 6 encodes a signal supplied from the sense amplifier 5 and outputs two-bit data items OUTA and OUTB.
The second column decoder 4 selects one of the bit-line selecting lines of the second set, in accordance with an address signal, and at the same time the first column decoder 3 selects one of the bit-line selecting lines of the first set. One of the bit lines is therefore selected and connected to the input SIN of the sense amplifier 5. Similarly, the row decoder 2 selects one of the word lines, in accordance with the address signal. As a result, the power-supply voltage Vdd is applied to the gate of the memory cell connected to the bit line and the word line which have been selected. For example, if the bit-selecting lines L1 and C1 and the word line W1 are selected, the data stored in the memory cell M1 will be read out.
FIG. 50 is a sense amplifier which may be used as the sense amplifier 5 in the conventional multi-level ROM of FIG. 49. This sense amplifier comprises two P-channel transistors Tr1 and Tr2 and three inverter circuits IN1, IN2 and IN3. The transistors Tr1 and Tr2 are connected in series, between a power-supply terminal Vdd and an input terminal SIN. The inverter circuits IN1, IN2 and IN3 are connected in parallel to the drain and gate of the transistor Tr1 and set at different reference potentials to discriminate the level of the signal supplied to the input terminal SIN. The potential applied to the input terminal SIN is determined by the current Icell which is to supplied to the memory cell selected. This is because, as has been described, the memory cells of the array 1 are of four types M00, M01, M10 and M11 which have different threshold voltages V1, V2, V3 and V4, respectively.
FIG. 51 is a diagram representing the relationship between the various potentials at the terminal SIN, on the one hand, and the reference potentials of the inverter circuits IN1, IN2 and IN3, on the other hand. Based on this relationship the inverter circuits IN1, IN2 and IN3 can detect the voltage generated at the input terminal SIN in accordance with the memory cell selected. The inverters IN1, IN2 and IN3 output signals DAi, DBi and DCi, respectively.
The signals DAi, DBi and DCi output from the sense amplifier 5 are input to the output circuit 6. The output circuit 6 has the structure shown in FIG. 52. As can be understood from FIG. 52, the circuit 6 converts the signals DAi, DBi and DCi to two-bit data items OUTA and OUTB. The algorithm for this conversion is shown in the following Table 1.
TABLE 1 ______________________________________ Memory cell DAi DBi DCi OUTA OUTB ______________________________________ M00 0 0 0 0 0 M01 1 0 0 0 1 M10 1 1 0 1 0 M11 1 1 1 1 1 ______________________________________
Thus can the data be read from the multi-level ROM. In the multi-level ROM ;shown in FIG. 48, the data is sensed by detecting one of four different voltages obtained by dividing the difference between the power-supply voltage Vdd and the ground potential applied the selected memory cell. The difference between the voltages read from the memory cell is small, and the reading margin is proportionally small. Furthermore, the difference between the currents Icell flowing through the memory cells is smaller than in a memory storing binary data. Therefore it is difficult to determine the best possible characteristic for the transistor Tr1 functioning as a load through which the currents Icell eventually flows. The voltages which the inverters IN1, IN2 and IN3 output by dividing the output voltage of the transistor Tr1 are inevitably not balanced, reducing the reading margin. Consequently, data may not be correctly read from any selected memory cell.
To store three-bit data, such as "000" or "010" into one memory cell, eight potentials need to be provided by dividing the difference between the voltage VIN applied to each memory cell and the ground potential GND. In this case, the reading margin is still smaller.
The more bits each memory cell of a memory stores, the more sense amplifiers the reading circuit of the memory must have in order to sense and read different data items. This results in an increase in the complexity of the circuit pattern of the memory as a whole also an increase in the peak current in the memory.